Intel Reports Good Progress on Intel 4 Process Node at IEEE Symposium

Intel Reports Good Progress on Intel 4 Process Node at IEEE Symposium

Intel Reports Good Progress on Intel 4 Process Node at IEEE Symposium

This week, Intel will present five papers at the 2022 IEEE Symposium on VLSI Technology & Circuits (VLSI) detailing the company’s progress with Intel 4, the semiconductor process technology formerly known as 7nm. Intel 4 is a transition process for Intel. It is the first Intel process node to use EUV (extreme ultraviolet, i.e. soft X-rays) lithography instead of deep UV immersion lithography. The advancements made in the Intel 4 process support Moore’s Law by doubling the achievable transistor density over Intel 7, the process node previously known as 10nm Enhanced Super Fin (10ESF). The Intel 4 process provides a 20% performance gain over chips made with the Intel 7 process while operating at the same power level. Alternatively, you can get 40% power savings with Intel 4 at the same level of performance as the previous process node.

Intel has been on its competitive footing in recent years as Intel TD (Technology Development) has delayed the use of EUV lithography longer than it should have. The idea was to delay the use of expensive EUV steppers for as long as possible to minimize production costs. By trying to stick with immersion lithography at one more node, Intel 7, Intel lost performance parity with its main production competitors. Now the company is all-in on EUV thanks to Pat Gelsinger’s aggressive stance. Intel 4 will be the company’s first manufacturing hub to fully embrace EUV.

Ben Sell, a VP of TD at Intel, is the lead author of one of five Intel 4 VLSI symposium papers entitled “Intel 4 CMOS Technology with Advanced FinFET Transistors Optimized for High Density and High Performance Computing.” Speaking ahead of the event, Sell said Intel 4 is not only reducing feature sizes, but is also using EUV to simplify process technology by reducing the complexity and cost of creating each on-chip layer.

With the feature sizes being drawn, deep UV immersion lithography requires multiple patterns to achieve the desired feature density. This is because the dimensions of the features drawn are much smaller than the wavelengths of light used. The Intel 4 process requires immersion lithography to expose the wafer through five different masks to create just one layer, while EUV requires only one mask due to the much shorter wavelengths of light used. So, while an EUV process layer costs more than a layer created with immersion lithography, due to the enormous purchase and operating costs of an EUV stepper, the cost for one EUV process layer is less than the five passes it takes to produce that same process. chip layer with immersion lithography.

The image below summarizes some of Intel 4’s scaling improvements over Intel 7:

As the picture shows, individual features – including the contacted port pitch, the fin pitch, and the connecting pitch – have all been shrunk. Additionally, a previously announced innovation for this process node appears as pink shaded rectangles in the above image. Those rectangles represent “dummy gates,” which are needed to electrically isolate adjacent FinFETs. With the transistor orientation shown in the image above, the dummy gates separate FinFETs positioned left and right. Previous Intel process nodes required a pair of dummy gates per transistor, so there were two dummy gates between each FinFET. For Intel 4, adjacent transistors share one dummy port, reducing the number of space-consuming separators by half.

Another important factor in downsizing is the use of three fins per FinFET transistor for the Intel 4 process versus four fins per transistor for the Intel 7 process. (Fins appear as horizontal gray rectangles in the image above.) Normally, using fewer, smaller fins would decrease FinFET performance because, all other things being equal, fewer and thinner fins increase the transistor’s channel resistance. Ideally, that resistance should be as low as possible.

However, Sell explained that Intel 4 reduces the number of fins needed per transistor by using “enhanced copper” (cobalt-clad copper) to reduce the trace impedance in the chip’s lower metal signal layers. Along with the additional capacity reduction that comes with scaling up, Intel was able to reduce the number of fins per transistor in the Intel 4-cell library without compromising performance. The net result of these innovations is to double the number of transistors per square millimeter for chips made with Intel 4 versus Intel 7. Doubling the number of transistors from one node to the next is the original definition of Moore’s Law.

Sell ​​said Intel Foundry Services (IFS) customers will have access to the Intel 4 process, but that IFS is really focusing on the successor process node, Intel 3. He also said chips developed for the Intel 4 process node easy port to Intel 3, by design. Intel will use even more EUV lithography steps in the Intel 3 process and will create a denser, powerful cell library specifically for that process node.

However, the Intel 3 process node is itself an intermediate step. Intel 20A, the first of the company’s “Angstrom Era” nodes, will ditch the obsolete FinFETs in favor of the even more three-dimensional RibbonFET transistors, which other semiconductor manufacturers call GAA (gate all around) transistors. RibbonFETs will again significantly increase transistor density by stacking multiple transistor channels (ribbons) vertically on top of each other instead of laying channel fins side by side as with FinFETs.

RibbonFETs exhibit improved transistor performance over FinFETs because the RibbonFET gate completely surrounds the channel. FinFET gates only contact the channel on three or four sides. Consequently, RibbonFET gates are better at controlling the current through the transistor, resulting in better performance. For reference, the much older planar FET gates only made contact with one of the four sides of the transistor channel, so FinFETs were a real improvement when they first entered production a decade ago.

Intel 20A will also be the company’s first process node to move the on-chip power distribution network (PDN) from the top of the chip to the bottom of the chip — the back of the wafer — which should significantly reduce impedances and improve performance. PDN’s performance while simplifying signal routing on the top metal layers of the chip by making more space available for signal wires in the metal stack. Intel has named this rear PDN technology “PowerVia”, which is a more expensive approach to making a PDN because it requires the creation of nano TSVs (through silicon vias) in the wafer. Innovations such as RibbonFETs and PowerVia add process steps and thereby increase the manufacturing cost per wafer, but that’s the price to pay to keep Moore’s law alive.

Sell ​​said the Intel 4 process will be ready for production in the second half of 2022. This process node is associated with Intel’s 14e-generation Meteor Lake client CPU architecture, expected to appear as production chips in Q2 or Q3 of 2023. Intel will discuss Meteor Lake at its upcoming Hot Chips 34 conference in August. The Intel 4 process node will also be used to create compute tiles (chiplets) for the company’s Granite Rapids CPUs, which target data center servers.